Exploring redundant arithmetics in computer-aided design of arithmetic datapaths

摘要

The rapid pace of technological evolution places a substantial amount of pressure on minimizing the time-to-market for integrated circuit designers. Such pressure on the design cycle combined with strict performance constraints makes the use of computer-aided design tools mandatory. In this context, CAD tools that improve performance in terms of delay, area or power consumption are of interest. In this paper, we present a design environment that is dedicated to arithmetic datapath design support. This environment consists of the following elements: (1) Stratus: a language that is dedicated to the parameterized generation of VLSI modules and that allows several levels of abstraction; (2) ArithLib: a library of parameterized arithmetic IP-block generators; and (3) several optimization algorithms that choose the best architecture for each arithmetic operator of a datapath, given an optimization goal. These algorithms consider binary arithmetic as well as redundant arithmetic, given the good intrinsic performance of redundant architectures. In addition, experimental results are presented.