Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing

摘要

This paper proposes a standard-cell based memory (SCM) as an alternative to a traditional on-chip SRAM for near-threshold voltage computing. It focuses on area- and energy-efficiency using minimum height standard-cells. Unlike conventional SCMs, the proposed SCM has standard-cells with a minimum possible cell height allowed by the logic design rule of the target technology. This paper also presents energy efficient readout and write schemes for reducing dynamic energy consumption. Post layout simulation using a 65-nm FD-SOI technology shows that the proposed SCM achieves area efficiency of 6.82 mu m(2) per bit (682F(2) per bit), which is 20% less than that of the state of the art SCMs. The results also show that the energy consumption of the proposed SCM is 31% less than that of the state of the art low voltage SRAMs.