Handling Multiple Clock Domains in Scan Design

摘要

Many of today's complex chips include multiple clock domains. Knowing how to identify and correct any problems that occur in the scan chains within these clocks is essential. As designs grow larger, the process of testing complex chips becomes increasingly difficult. The need to incorporate more than one clock domain within a system often exacerbates these difficulties. Handling numerous domains in the test cycle can lead to problems when the silicon returns from the fab. Properly understanding the relationship between scan design and multiple clock domains helps to ensure a circuit that functions correctly.