高速数据的跨时钟域处理方法及验证

摘要

In order to solve the image acquisition and mismatch transmission rate in high speed image acquisition system,the internal storage resources of FPGA is used and the principles of asynchronous FIFO is introduced to analyze the meta-stable state and full/empty signal to achieve asynchronous FIFO using Verilog HDL and QuartusII tools macro module.The results show that the cross clock domain of high speed data transmission is achieved,when the write clock is 82 MHz and the read clock is 50 MHz.%为了解决高速相机数据采集和处理速率的不匹配问题，利用现场可编程逻辑门阵列内部存储资源，研究了高速、大容量异步 FIFO 的工作原理，提出了异步 FIFO 工作中的亚稳态和空／满标识问题，采用 Verilog HDL 编写时序代码和 QuartusII 工具宏模块定制两种方法实现异步 FIFO．研究结果表明：当写入时钟为82 MHz，异步 FIFO 可实现的读出时钟为50 MHz，实现了高速数据采集和传输系统的跨时钟域处理．