Clock domain crossing formal verification: a meta-model

摘要

In the context of industrial designs, circuits are based on many IPs defined on their own clock domain. It leads to globally asynchronous locally synchronous designs. The transmission of data between clock domains must be carefully verified to avoid metastability, inconsistency and data loss. EDA tools propose a strategy based on a minimal detection of a synchronizer structure. Conversely, in this paper we propose a meta-model of synchronizer that speeds up the proof and ensures its better automation.