Asymmetry Mitigation in IEEE 802.3 Ethernet for High-Accuracy Clock Synchronization

摘要

Clock synchronization is one of the basic services in a distributed network as it enables a palette of services, such as synchronized measurements and actions, or time-based access to shared communication media. The IEEE 1588 standard defines the precision time protocol (PTP) that is capable of synchronizing multiple slave clocks to a master by means of synchronization event messages. Supported by the recent advances in hardware timestamping, PTP devices are ready for achieving synchronization accuracies in the subnanosecond range. The accuracy of practical synchronization systems is, however, often bounded by the inability to determine and compensate for asymmetric line delays leading to unresolvable clock offsets. Although IEEE 1588 version 2008 is able to compensate for known asymmetry, no specific measures to estimate the asymmetry are defined in the standard. In this paper, we present a solution to determine the asymmetry for 100Base-TX networks based on line swapping and highly accurate timestamping. When the presented approach is used within the startup procedure of an Ethernet link, the synchronization offsets can be minimized while the operation of the network is not impaired. We show by an FPGA-based prototype system that our approach is able to reduce the clock offset from multiple nanoseconds to below 120 ps.