Reducing losses in three-phase PWM pulsed DC-link voltage-type inverter systems

摘要

This paper deals with pulsewidth modulation (PWM) strategies that synchronize clamped voltage segments using the current peak in the corresponding phases of a three-phase quasi-resonant DC-link (QRDCL) voltage inverter. It is shown that, instead of employing lookup tables, these strategies can be easily implemented by using, the concept of hybrid modulation in this type of pulsed DC-link voltage (PDCLV) inverter. In fact, such concept leads to a systematic and straight approach to the generation of any continuous or discontinuous PWM strategy. A topology that is shown to produce fewer losses than either PDCLV inverters or the hard-switched inverter version is used to compare the losses produced when the two strategies discussed in the paper are employed. Simulation and experimental results confirm the validity of the proposed technique.