DC-Offset Rejection in Phase-Locked Loops: A Novel Approach

摘要

Phase-locked loops (PLLs) are undoubtedly the most popular synchronization technique in the power and energy applications. A challenging problem of designing PLLs is the presence of dc offset in their input, which causes fundamental-frequency oscillatory errors in their estimated quantities. In this paper, a novel method to tackle this problem is presented. The effectiveness of this approach is verified through numerical results.