DC-Offset Rejection Approaches for Single-Phase Frequency-Locked Loop

摘要

Frequency-fixed implementation of a single-phase frequency-locked loop (FLL) has been reported to enhance the FLL's dynamic performance when the supply voltage is sinusoidal or harmonically distorted. However, when dc-offset is present in the supply voltage, a dc-offset rejection (DC-OR) stage is usually incorporated in the FLL implementation. How the DC-OR stage affects the FLL's dynamic performance is one gap that exists in the literature. Consequently, this paper focuses on evaluating the effect of the DC-OR stage on the FLL's performance by coupling and decoupling the DC-OR stage and the FLL. Decoupling is achieved by fixing the frequency of the DC-OR stage at the supply voltage's nominal frequency. However, this introduces a phase-offset error at the FLL output when the supply voltage experiences a frequency deviation. To address this issue, a phase-offset compensation approach is developed. Through experimental studies, accuracy of the phase-offset compensation approach is verified. Furthermore, it is shown that farther the point of decoupling and the FLL output, faster is the FLL response. Therefore, a frequency-adaptive FLL can achieve faster response than its frequency-fixed counterpart when the effect of dc-offset rejection stage is considered.