Selective Clock Suppression of Protocol Modules for a Low Power Protocol Converter

摘要

This letter presents a method for reducing power dissipation in a protocol converter. The communication protocol of a VLSI chip hierarchically consists of several sub- protocols and only one of them can be actively working at any given time. In general, protocol converters are implemented by dual protocols of the initially given protocols which are to be in- terfaced. If the duals of those sub-protocols are implemented in separate modules, we can separate active modules and inactive modules on the fly since only one of the modules can be active at a time.