On Acceleration of Test Points Selection for Scan-Based BIST

摘要

This paper presents an acceleration of test points selection for circuits designed by a full-scan based BIST scheme. In order to accelerate the test points selection based on cost min- imization, and reflecting random pattern testability, we introduce three techniques, the simultaneous selection of plural test points, the simplified selection of test points by the cost reduction fac- tor, and the reduction of the number of test point candidates. We implement a program based on the proposed techniques and eval- uate its efficiency experimentally using large scale circuits (26 k- 420 k gates).