Power Estimation and Reduction of CMOS Circuits Considering Gate Delay

摘要

In this paper, we propose a method, called PORT- D, for optimizing CMOS logic circuits to reduce the average power dissipation. PORT-D is an extensional method of PORT. While PORT reduces the average power dissipation under the zero delay model, PORT-D reduces the average power dissipation by taking into account of the gate delay. In PORT-D, the average power dissipation is esti- mated by the revised BDD traversal method. The revised BDD tra- versal method calculates switching activity of gate output by con- structing OBDD' s without representing switching condition of a gate output. PORT-D modifies the circuit in order to reduce the average power dissipation, where transformations which reduce the average power dissipation are found by using permissible functions. Experi- mental results for benchmark circuits show PORT-D reduces the aver- age power dissipation more than the number of transistors. Further- more, we modify PORT-D to have high power reduction capability. In the revised method, named PORT-MIX, a mixture strategy of PORT and PORT-D is implemented. Experimental results show PORT-MIX has higher power reduction capability and higher area optimization ca- pability than PORT-D.