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首页> 外文期刊>IEICE Transactions on fundamentals of electronics, communications & computer sciences >Intra-Die Spatial Correlation Extraction with Maximum Likelihood Estimation Method for Multiple Test Chips
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Intra-Die Spatial Correlation Extraction with Maximum Likelihood Estimation Method for Multiple Test Chips

机译:最大似然估计法在多个测试芯片上进行模内空间相关提取

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摘要

In this paper, a novel intra-die spatial correlation extraction method referred to as MLEMTC (Maximum Likelihood Estimation for Multiple Test Chips) is presented. In the MLEMTC method, a joint likelihood function is formulated by multiplying the set of individual likelihood functions for all test chips. This joint likelihood function is then maximized to extract a unique group of parameter values of a single spatial correlation function, which can be used for statistical circuit analysis and design. Moreover, to deal with the purely random component and measurement error contained in measurement data, the spatial correlation function combined with the correlation of white noise is used in the extraction, which significantly improves the accuracy of the extraction results. Furthermore, an LU decomposition based technique is developed to calculate the log-determinant of the positive definite matrix within the likelihood function, which solves the numerical stability problem encountered in the direct calculation. Experimental results have shown that the proposed method is efficient and practical.
机译:在本文中,提出了一种新的管芯内部空间相关性提取方法,称为MLEMTC(多个测试芯片的最大似然估计)。在MLEMTC方法中,通过将所有测试码片的单个似然函数集相乘来制定联合似然函数。然后使该联合似然函数最大化,以提取单个空间相关函数的唯一一组参数值,该参数值可用于统计电路分析和设计。此外,为了处理测量数据中包含的纯随机分量和测量误差,在提取中使用了空间相关函数和白噪声的相关性,从而显着提高了提取结果的准确性。此外,开发了一种基于LU分解的技术来计算似然函数内正定矩阵的对数行列式,从而解决了直接计算中遇到的数值稳定性问题。实验结果表明,该方法是有效和实用的。

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