Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring

摘要

A probing front end circuit (PFE) senses and digitizes voltage noises at in-circuit locations on such as power supply wiring and substrate taps in a chip, with the simplest circuit construction only with a source follower or a unity gain buffer, followed by a latch comparator. The PFE with 2.5 V I/O transistors in a 65 nm CMOS technology node demonstrates 9.0 ENOB and 60.7 dB SFDR in equivalent sampling at 1.0 Gs/s, for a sinusoidal waveform of 10 MHz with 200 mV peak-to-peak amplitude. Behavioral modeling of an entire waveform acquisition system using PFEs includes the statistical variations of reference voltage and sampling timing. The simulation quantitatively explains the measured dynamic properties of on-chip noise monitoring, such as the AC response in SNDR and digitizing throughputs, with the clear dependency on the frequency and amplitude of input waveforms.