Area Efficient ΔΣ Modulator Based on Power-Delay and Area Product for D/A Conversion

摘要

An efficient way to optimize the hardware consumption in a low-voltage ΔΣ modulator for D/A converters is described. The modulator employs a ROM selection scheme for multiplications and the new buffer-and-routing ROM structure to minimize the hardware consumption. Furthermore, a guideline of the power-delay-and-area product (PDAP) for compelling issues such as power dissipation, delay time, and chip area consumption in the modern digital-circuit design is proposed. After the validity of the concept has been proved in comparison with that of the conventional guideline of the power-delay product in several behavioral blocks, it was employed in the circuit design. Fabricated in a standard digital 0.35-μm CMOS technology, the modulator achieves a signal-to-noise ratio (SNR) of 96 dB with an oversampling ratio of 256 under the supply of 2.0 V.