首页> 外文期刊>IEICE Transactions on Electronics >An 8b 220 MS/s 0.25 μm CMOS Pipeline ADC with On-Chip RC-Filter Based Voltage References
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An 8b 220 MS/s 0.25 μm CMOS Pipeline ADC with On-Chip RC-Filter Based Voltage References

机译:具有基于片内RC滤波器的电压基准的8b 220 MS / s 0.25μmCMOS流水线ADC

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摘要

This work proposes an 8b 220 MS/s 230 mW 3-stage pipeline CMOS ADC with on-chip filters for temperature- and power supply- insensitive voltage references. The proposed RC low-pass filters reduce reference settling time at heavy R&C loads and improve switching noise performance without conventional off-chip bypass capacitors. The prototype ADC fabricated in a 0.25 μm CMOS occupies the active die area of 2.25 mm~2 and shows the measured DNL and INL of maximum 0.43 LSB and 0.82 LSB, respectively. The ADC maintains the SNDR of 43 dB and 41 dB up to the 110 MHz input at 200 MS/s and 220 MS/s, respectively, while the SNDR at the 500 MHz input is degraded as much as only 3 dB than the SNDR at the 110 MHz input.
机译:这项工作提出了一个8b 220 MS / s 230 mW的3级流水线CMOS ADC,带有片上滤波器,用于对温度和电源不敏感的电压基准。拟议的RC低通滤波器在没有传统的片外旁路电容器的情况下,减少了R&C负载较大时的基准建立时间,并改善了开关噪声性能。以0.25μmCMOS制成的ADC原型的有源管芯面积为2.25 mm〜2,测得的DNL和INL分别为最大0.43 LSB和0.82 LSB。 ADC分别以200 MS / s和220 MS / s的速率分别在110 MHz输入时将SNDR维持在43 dB和41 dB,而在500 MHz输入时,SNDR的降幅仅为SNDR时的3 dB。 110 MHz输入。

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