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An 8b 220 MS/s 0.25 /spl mu/m CMOS pipeline ADC with on-chip RC-filter based voltage references

机译:具有基于片内RC滤波器的电压基准的8b 220 MS / s 0.25 / spl mu / m CMOS流水线ADC

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This work proposes an 8b 220 MS/s 230 mW 3-stage pipeline CMOS ADC with on-chip filters for temperature- and power supply-insensitive voltage references. The proposed RC low-pass filters reduce reference settling time at heavy R & C loads and improve switching noise performance without conventional off-chip bypass capacitors. The prototype ADC fabricated in a 0.25 /spl mu/m CMOS occupies the active die area of 2.25 mm/sup 2/ and shows the measured DNL and INL of maximum 0.43 LSB and 0.82 LSB, respectively. The ADC maintains the SNDR of 43 dB and 41 dB up to the 110 MHz input at 200 MS/s and 220 MS/s, respectively, while the SNDR at the 500 MHz input is degraded as much as only 3 dB than the SNDR at the 110 MHz input.
机译:这项工作提出了8B 220 MS / S 230 MW 3级流水线CMOS ADC,用于片上过滤器,用于温度和电源不敏感电压参考。所提出的RC低通滤波器在重型R&C负载下减少参考稳定时间,并在没有传统的片外旁路电容的情况下提高开关噪声性能。在0.25 / SPL MU / M CMOS中制造的原型ADC占用2.25mm / sup 2 /的有源模面积/并分别显示测量的DNL和INL最大为0.43LSB和0.82LSB。 ADC将43 dB的SNDR保持在200 ms / s和220 ms / s的110 MHz输入,而500 MHz输入的SNDR分别降低,只能超过3dB,而​​不是SNDR 110 MHz输入。

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