A CAD-Based Low-Power Design Methodology for Very High-Speed Si Bipolar Standard Cell LSIs

摘要

A computer-aided low-power design methodology for very high-speed Si bipolar standard cell LSI is described. In order to obtain Gbit/s-speed operation, it features a pair of differential clock channels inside cells and a highly accurate static timing analysis for back annotation. A newly developed CAD-based power optimization scheme minimizes cell currents while maintaining circuit speed. A 5.6k gate SDH signal-processing LSI operating at 1.6Gbit/s with only 3.9 W power consumption demonstrates the effectiveness of this design technology.