Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis

摘要

Random variations in I_d-V_g characteristics of MOS transistors in an LSI chip are shown to be concisely characterized by using only 3 transistor parameters (V_(th), β_0,v_(sat)) in the MOS level 3 SPICE model. Statistical analyses of the transistor parameters show that not only the threshold voltage variation, ΔV_(th), but also the current factor variation, Δβ_0, independently induces I_d-variation, and that Δβ_0 is negatively correlated with the saturation velocity variation, Δv_(sat). Using these results, we have proposed a simple method that effectively takes the correlation between parameters into consideration when creating statistical model parameters for designing a circuit. Furthermore, we have proposed a sensitivity analysis methodology for estimating the process window of SRAM cell operation taking transistor variability into account. By applying the concise statistical model parameters to the sensitivity analysis, we are able to obtain valid process windows without the large volume of data-processing and long turnaround time associated with the Monte Carlo simulation. The process window was limited not only by ΔV_(th), but also by Δβ_0 which enhanced the failure region in the process window by 20%.