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A Fundamental Analysis of Single Event Effects on Clocked CVSL Circuits with Gated Feedback

机译:具有门控反馈的时钟CVSL电路的单事件影响的基础分析

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摘要

Clocked cascade voltage switch logic (C~2VSL) circuits with gated feedback were newly designed for synchronous systems. In order to investigate single event transient (SET) effects on the C~2VSL circuits, SET effects on C~2VSL EX-OR circuits were analyzed using SPICE. Simulation results have indicated that the C~2 VSL have increased tolerance to SET.
机译:带有门控反馈的时钟级联电压开关逻辑(C〜2VSL)电路是新设计用于同步系统的。为了研究单事件瞬态(SET)对C〜2VSL电路的影响,使用SPICE分析了SET对C〜2VSL EX-OR电路的影响。仿真结果表明,C〜2 VSL对SET的容忍度有所提高。

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