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On the New Stopping Criteria of Iterative Turbo Decoding by Using Decoding Threshold

机译:使用解码阈值的新迭代Turbo解码停止条件

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摘要

Although many stopping methods of iterative decoding have been discussed in the literature extensively, many of them only focus on the solvable decoding (information is enough for successful decoding). In this paper, we discuss the limitation of the decoding ability based on the extrinsic information transform (EXIT) chart. Then, we propose a new information measurement by using cross correlation to predict the decoding threshold. Moreover, we propose two early termination (ET) schemes (ET-I and ET-II) based on the predicted decoding threshold. The iterative decoding can stop in either high-signal-to-noise ratio (SNR) situations where the decoded bits are highly reliable (solvable decoding), or low-SNR situations where the decoder already has no capability to decode (unsolvable decoding). The simulation results show that the reduced iterations due to the ET-I scheme almost will not affect the SNR performance, and the ones due to the ET-II scheme can still satisfy the requirement of the specification. Based on our analysis and simulation results, we can further modify the conventional GENIE chart by considering the decoding threshold. By using our new ET concepts, the previous stopping techniques can also be modified to stop in low-SNR situations. The ET property for the iterative decoding can help reduce the unnecessary iterations, so as to save computational complexity and power consumptions in digital signal processors (DSPs) or application-specific integrated circuits (ASICs) in mobile handsets.
机译:尽管在文献中已经广泛讨论了迭代解码的许多停止方法,但是它们中的许多仅集中于可解解码(信息足以成功解码)。在本文中,我们基于外部信息变换(EXIT)图讨论了解码能力的局限性。然后,我们提出了一种使用互相关来预测解码阈值的新信息测量方法。此外,我们基于预测的解码阈值提出了两种提前终止(ET)方案(ET-I和ET-II)。迭代解码可以在解码后的比特高度可靠(可解决解码)的高信噪比(SNR)情况下,或者在解码器已经不具备解码能力(无法解决的解码)的低SNR情况下停止。仿真结果表明,ET-I方案减少的迭代几乎不会影响SNR性能,而ET-II方案减少的迭代仍然可以满足规范要求。根据我们的分析和仿真结果,可以通过考虑解码阈值来进一步修改常规GENIE图。通过使用我们的新ET概念,还可以修改先前的停止技术以在低SNR情况下停止。迭代解码的ET属性可以帮助减少不必要的迭代,从而节省手机中数字信号处理器(DSP)或专用集成电路(ASIC)的计算复杂性和功耗。

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