The Grand Pareto: A Methodology for Identifying and Quantifying Yield Detractors in Volume Semiconductor Manufacturing

摘要

A method of communicating a unified pareto, we call "Grand Pareto," for technology-wide failure mechanisms that limit the profitability of a fabrication facility is presented. The Grand Pareto leverages multiple defect detection and isolation techniques in conjunction with state-of-the-art physical failure analysis and statistical yield analysis techniques to create a single message for the process community to drive the yield improvement efforts. The methodology has been successfully deployed at IBM where it has been assisting identification of key yield detractors for several high-end microprocessors in volume production