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首页> 外文期刊>Semiconductor Manufacturing, IEEE Transactions on >Modeling of Integrated Circuit Yield Using a Spatial Nonhomogeneous Poisson Process
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Modeling of Integrated Circuit Yield Using a Spatial Nonhomogeneous Poisson Process

机译:使用空间非均匀泊松过程的集成电路良率建模

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摘要

This paper proposes a new yield model for integrated circuits using a spatial point process. The defect density variation by location on a wafer is modeled by a spatial nonhomogeneous Poisson process. The intensity function of the yield model describes the defect pattern on wafers. As a result, the model differs from the existing compound Poisson yield models in its capability to describe the spatial defect distribution. Using model-based clustering, the defect clusters from assignable causes, which contain the information about the variations of manufacturing processes, can be classified from others. The proposed model considers the defect density variation among wafers and the impact of defect size on the probability of a defect causing the circuit failure. The performance of the new yield model is verified using simulated data and real data. Simulation results show that the new yield model performs better than a compound Poisson yield model.
机译:本文提出了一种采用空间点工艺的集成电路良率模型。通过空间非均质泊松过程对晶片上的缺陷密度变化进行建模。成品率模型的强度函数描述了晶圆上的缺陷图案。结果,该模型在描述空间缺陷分布的能力方面不同于现有的复合泊松屈服模型。使用基于模型的聚类,可以将来自可分配原因的缺陷聚类(包含有关制造过程变化的信息)进行分类。所提出的模型考虑了晶片之间的缺陷密度变化以及缺陷尺寸对缺陷引起电路故障的可能性的影响。使用模拟数据和真实数据验证了新收益模型的性能。仿真结果表明,新的收益模型的性能优于复合泊松收益模型。

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