Characterization of 4 Million Micro-Bump Interconnections at 7.6- Pitch for 3-D Stacked 16 Million Pixel Image Sensor

摘要

We developed and reported on a 3-D stacked CMOS image sensor (CIS) with a massive number of micro-bump interconnections placed at a narrow pitch between silicon substrates that pushes the envelope of CIS functions. The resistances of the interconnections were measured to be less than one hundredth of an ohm per bump with a test structure. There were, however, a small number of defective micro bumps with much higher impedance among the four million interconnections of the sensor. We developed a method for distinguishing defective interconnections from other defects and evaluated all interconnection resistances in a short amount of time with additional circuits in the CIS with reduced variable factors by using a modified current flow mode. This method makes it possible not only to identify defective interconnections but also to measure their impedances with less fluctuation.