Synchronous Double-Pumping Technique for Integrated Current-Mode PWM DC–DC Converters Demand on Fast-Transient Response

摘要

While the fast transient techniques have been extensively investigated, the research aiming at current-mode pulse width modulation (PWM) converters is relatively unexplored. This paper presents a synchronous double-pumping (SDP) technique for current-mode PWM dc-dc converters to achieve fast-transient response between different load conditions. The advantages and limitations of the existing conventional techniques are discussed and analyzed. With the proposed SDP technique, a nearly optimized recovery time speedup and voltage drop minimization for every different conventional current-mode converters can be obtained. The prototype chip was fabricated using a TSMC 0.35-μm CMOS process occupies the area of 2.242 mm2 including all bonding pads and ESD protection circuits. The output voltage ripple is measured about 15 mV in peak-to-peak value. The recovery time is 2.4 and 2.6 μs, respectively, in response to the 400-mA step-up and step-down load changes. Those are improved by a factor of 8.33 and 8.23, respectively.