Hybrid SVPWM Scheme to Minimize the Common-Mode Voltage Frequency and Amplitude in Voltage Source Inverter Drives

摘要

In this paper, a hybrid space vector pulsewidth modulation synthesis is proposed to lower the frequency and amplitude of the common-mode voltage (CMV). The conventional space vector pulsewidth modulation (SVPWM) techniques for inverters generate a high-frequency CMV. The CMV causes significant bearing current flowing through the path to the ground and leads to premature bearing failure, especially in high switching frequency drive systems. Furthermore, previously proposed CMV reduction studies focus on the reduction of CMV amplitude, leaving a high-frequency CMV. The proposed control algorithm divides each sector in the space vector hexagon into three segments based on the modulation index and the angle of the reference voltage vector. In each segment, the space vectors that produce minimal CMV are selected to synthesize the reference voltage vector. A fair comparison with the conventional CMV reduction methods is made by comparing the CMV characteristics, harmonic distortion factor, dc current ripple, and the switching losses for each method. Both simulation and experimental results have validated the effectiveness of the proposed approach.