A dual-port FASTBUS memory to test the L3 data acquisition system

摘要

A dual-port 0.25-Mbytes (64 K*32 bits) FASTBUS memory module is described which implements a large set of functions on the Crate Port, while the Cable Port is mainly used for data transfers. Both linear and circular FIFO-like modes are software-selectable. Two pointers are available for write and read operations, respectively. The memory, successfully used to test the L3 event builders, exhibits features of an interesting, general purpose, FASTBUS module for event buffering in large data acquisition systems.