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Study of a CMOS-JFET-bipolar radiation hard analog-digital technology suitable for high energy physics electronics

机译:适用于高能物理电子学的CMOS-JFET-双极辐射硬模数技术研究

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摘要

The authors present results obtained on a rad-hard mixed analog-digital technology that integrates monolithically complementary MOS (CMOS) transistors, complementary junction FETs (CJFETs), and complementary bipolar transistors (C-bipolars). This technology is expected to satisfy the hard constraints of Large Hadron Collider (LHC) detector electronics. These three families of transistors have been chosen to offer large flexibility of design. MOS and bipolar transistors provide electrical characteristics close to those of modern BiCMOS technologies and will allow the design on the same chip of both analog and digital fast rad-hard circuits. JFET transistors will permit designs of low-noise very rad-hard circuits for room or cryogenic temperature operation. The results show devices with rad-hard performances against neutrons and gamma particles in the range of 1*10/sup 14/ n/cm/sup 2/ (1 MeV) and 10 Mrads (SiO/sub 2/), well suited to LHC detector requirements. JFETs, which have shown a low sensitivity to protons (500 MeV) up to 1*10/sup 14/, are very rad-hard against ionizing dose as well as displacement damages.
机译:作者介绍了在抗辐射混合模拟数字技术上获得的结果,该技术集成了单片互补MOS(CMOS)晶体管,互补结FET(CJFET)和互补双极晶体管(C-双极)。该技术有望满足大型强子对撞机(LHC)检测器电子设备的严格限制。选择这三个晶体管系列可提供更大的设计灵活性。 MOS和双极晶体管提供的电气特性接近现代BiCMOS技术,并将允许在模拟和数字快速抗辐射电路的同一芯片上进行设​​计。 JFET晶体管将允许在室温或低温条件下设计低噪声,极抗辐射的电路。结果表明,对中子和伽玛粒子具有抗辐射性能的器件在1 * 10 / sup 14 / n / cm / sup 2 /(1 MeV)和10 Mrads(SiO / sub 2 /)的范围内LHC检测器要求。 JFET对质子(500 MeV)的灵敏度低至1 * 10 / sup 14 /,对离子化剂量和位移损伤非常抗辐射。

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