Single-Event-Upset Critical Charge Measurements and Modeling of 65 nm Silicon-on-Insulator Latches and Memory Cells

Heidel D. F.; Rodbell K. P.; Oldiges P.; Gordon M. S.; Tang H. H. K.; Cannon E. H.; Plettner C.

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Single-Event-Upset Critical Charge Measurements and Modeling of 65 nm Silicon-on-Insulator Latches and Memory Cells

机译：65 nm绝缘体上硅锁存器和存储单元的单事件重置临界电荷测量和建模

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摘要

Experimental and modeling results are presented on the critical charge required to upset exploratory 65 nm silicon-on-insulator (SOI) circuits. Using a mono-energetic, collimated, beam of particles the charge deposition was effectively modulated and modeled

机译：实验和建模结果显示了使探索性65 nm绝缘体上硅（SOI）电路所需的临界电荷。使用单能量准直的粒子束，电荷沉积得到有效调制和建模

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《IEEE Transactions on Nuclear Science》 |2006年第2006期|p.3512-3517|共6页
作者
Heidel D. F.; Rodbell K. P.; Oldiges P.; Gordon M. S.; Tang H. H. K.; Cannon E. H.; Plettner C.;
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原文格式 PDF
正文语种 eng
中图分类原子能技术;
关键词
SRAM chips; alpha-particle effects; charge measurement; field effect logic circuits; field effect memory circuits; flip-flops; integrated circuit modelling; ion beam effects; radiation hardening (electronics); silicon-on-insulator; 65 nm; SOI; critical charge measur;

机译：SRAM芯片;阿尔法粒子效应;电荷测量;场效应逻辑电路;场效应存储电路;触发器;集成电路建模;离子束效应;辐射硬化（电子）;绝缘体上硅;65 nm;SOI;临界电荷测量;

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1. Low-Energy Proton-Induced Single-Event-Upsets in 65 nm Node, Silicon-on-Insulator, Latches and Memory Cells [J] . Rodbell K. P., Heidel D. F., Tang H. H. K., IEEE Transactions on Nuclear Science . 2007,第6期

机译：65 nm节点，绝缘体上硅，锁存器和存储单元中的低能质子诱导的单事件扰动
2. Modeling Single-Event Upsets in 65-nm Silicon-on-Insulator Semiconductor Devices [J] . KleinOsowski A., Oldiges P., Williams R. Q., IEEE Transactions on Nuclear Science . 2006,第期

机译：在65 nm绝缘体上硅半导体器件中模拟单事件扰动
3. Alpha-Particle, Carbon-Ion and Proton- Induced Flip-Flop Single-Event-Upsets in 65 nm Bulk Technology [J] . Wissel L., Cannon E. H., Heidel D. F., IEEE Transactions on Nuclear Science . 2008,第期

机译：采用65 nm批量技术的Alpha-Particle，碳离子和质子诱导的触发器单事件翻转
4. Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process [C] . Kodai Yamada, Haruki Maruoka, Jun Furuta, International Reliability Physics Symposium . 2018

机译：在65 nm FDSOI工艺中，通过具有堆叠结构的锁存器评估了NMOS和PMOS晶体管对软错误的敏感性
5. Physics based modeling of the charging dynamics in silicon nanocrystal non-volatile flash memory cell [D] . Singaraju Venkata Sai, Pavan Kumar 2007

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Single-Event-Upset Critical Charge Measurements and Modeling of 65 nm Silicon-on-Insulator Latches and Memory Cells

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