首页> 外文期刊>Nuclear Science, IEEE Transactions on >Fully Digital FPGA-Based Data Acquisition System for Dual Head PET Detectors
【24h】

Fully Digital FPGA-Based Data Acquisition System for Dual Head PET Detectors

机译:基于全数字FPGA的双头PET检测器数据采集系统

获取原文
获取原文并翻译 | 示例

摘要

We present the development of a new fully digital, flexible, cost-efficient data acquisition system (DAQ) suitable for dual head Positron Emission Tomography (PET) scanners for small animal imaging applications. A free-running 12 bit octal channel Analog to Digital Converter (ADC), with 65 MHz sampling rate, was used for the digitization of the detector signals. The digitized data were fed into a Spartan 6 Field Programmable Gate Array (FPGA) for event processing. An embedded system was developed for the acquisition, using Xilinx’s Embedded Development Kit (EDK) and Microblaze processor. A digital version of the Constant Fraction Discriminator (CFD) method was implemented in the FPGA, in order to achieve higher time resolution than the ADC sampling period, eliminating the need of an external mixed-signal device. The obtained information using FPGA includes: event timing, energy determination-discrimination, position determination and coincidence processing. The online processing of potential coincident events, significantly reduces the amount of data that will be transmitted to the computer. Coincident events are written temporarily to an external memory provided on a development board and are transferred to a Personal Computer (PC), via Ethernet link, for image reconstruction. Minimal post processing of the data is required prior to reconstruction. A small detector pair consisting of a BGO array coupled to a Position Sensitive Photomultiplier Tube (PSPMT) was used for the evaluation of the readout system. Obtained results prove that the proposed architecture can be used for the readout of dual head PET detectors for small animal imaging applications.
机译:我们介绍了一种适用于小型动物成像应用的双头正电子发射断层扫描(PET)扫描仪的新型全数字化,灵活,经济高效的数据采集系统(DAQ)的开发。一个自由运行的12位八通道八通道模数转换器(ADC),采样率为65 MHz,用于检测器信号的数字化。数字化的数据被馈送到Spartan 6现场可编程门阵列(FPGA)中进行事件处理。使用Xilinx的嵌入式开发套件(EDK)和Microblaze处理器,开发了一个用于收购的嵌入式系统。在FPGA中实现了恒定分数鉴别器(CFD)方法的数字版本,以实现比ADC采样周期更高的时间分辨率,从而无需外部混合信号器件。使用FPGA获得的信息包括:事件定时,能量确定-区分,位置确定和重合处理。潜在的同步事件的在线处理大大减少了将要传输到计算机的数据量。巧合事件被临时写入开发板上提供的外部存储器,并通过以太网链接传输到个人计算机(PC),以进行图像重建。在重建之前,需要对数据进行最少的后处理。由耦合到位置敏感光电倍增管(PSPMT)的BGO阵列组成的小型检测器对用于评估读出系统。所得结果证明,该结构可用于小型动物成像应用的双头PET探测器的读取。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号