Comprehensive Study of Pi-Gate Nanowires Poly-Si TFT Nonvolatile Memory With an HfO $_2$ Charge Trapping Layer

摘要

This work demonstrates the feasibility of a polycrystalline silicon thin-film transistor (poly-Si TFTs) nonvolatile memory (NVM) that utilizes a Pi-shaped gate (Pi-gate) and multiple nanowire channels with a HfO $_2$ charge-trapping layer. The TFT NVM with the Pi-gate nanowires (NWs) structure has a higher program/erase (P/E) efficiency than that of the conventional single-channel TFT NVM; the memory window can achieve 2.3 V, only needs a programming time of 1 μs. This high P/E efficiency follows from the improved gate control of the Pi-gate structure. A Pi-gate NWs poly-Si TFT NVM with a Si $_3$N$_4$ charge-trapping layer was also fabricated. Since HfO$_2$ has a deeper conduction band than Si $_3$N$_4$, the device with the HfO$_2$ charge-trapping layer has a higher programming efficiency and the better retention characteristics than that with the Si $_3$N$_4$ charge-trapping layer. Additionally, the high programming efficiency allows the device with the HfO$_2$ charge-trapping layer to undergo more P/E cycles than that with the Si$_3$ N$_4$ charge-trapping layer.