A 3–10-GHz Low-Power CMOS Low-Noise Amplifier for Ultra-Wideband Communication

摘要

A 90-nm CMOS low-noise amplifier (LNA) for 3–10-GHz ultra-wideband (UWB) applications is presented. The circuit adopts a single-ended dual-stage solution. The first stage is based on a current-reuse topology and performs UWB (3–10 GHz) input matching. The second stage is a cascode amplifier with resonant load to enhance gain and reverse isolation. Thanks to both the circuit solution and design approach, the LNA provides input matching, low noise, flat gain, and small group-delay variation in the UWB frequency range at minimum power consumption. The design is also conceived to cope with application issues such as low-cost off-chip interfaces and electrostatic discharge robustness. Measurements exhibit a 12.5-dB power gain in a 7.6-GHz 3-dB bandwidth, a minimum noise figure of 3 dB, a reverse isolation better than 45 dB up to 10.6 GHz, and a record small group-delay variation of $pm$12 ps. The LNA draws 6 mA from a 1.2-V power supply.