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A Doherty Architecture With High Feasibility and Defined Bandwidth Behavior

机译:具有高可行性和已定义带宽行为的Doherty架构

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摘要

This paper presents a complete and rigorous theoretical investigation of a Doherty architecture with a novel output combining network. The benefits in terms of bandwidth and feasibility held by the proposed topology are investigated and compared with the conventional one. In particular, the theoretical analysis demonstrates that the proposed output combiner allows to implement a Doherty amplifier with defined bandwidth (narrower or broader) without worsening in performances. Moreover, the proposed solution results in a more feasible structure with respect to the classical one, especially when high output power levels are sought. The theoretical results are validated through the design and realization of a prototype based on commercial GaN active devices. Experimental results show 42-dBm output power and 65% peak efficiency with a flat behavior in the 1.95–2.25-GHz frequency band (i.e., 14% of relative bandwidth) under continuous wave signal. Moreover, 50% average efficiency at 38-dBm average output power with $-$ 45 dBc of adjacent channel power ratio is demonstrated under 5-MHz 3GPP driving signal using a simple polynomial digital pre-distortion.
机译:<?Pub Dtl?>本文提出了具有新颖输出组合网络的Doherty体系结构的完整而严格的理论研究。研究了所提出的拓扑在带宽和可行性方面的优势,并将其与常规拓扑进行了比较。具体而言,理论分析表明,所提出的输出组合器可以实现具有定义带宽(更窄或更宽)的Doherty放大器,而不会降低性能。此外,所提出的解决方案导致相对于经典解决方案而言更可行的结构,尤其是在寻求高输出功率水平时。通过设计和实现基于商用GaN有源器件的原型,验证了理论结果。实验结果表明,在连续波信号下,在1.95–2.25 GHz频带(即相对带宽的14%)下,输出功率为42 dBm,峰值效率为65%,性能平坦。此外,在38 dBdBm的平均输出功率下,采用 $-$ 45 dBc的相邻信道功率比,得出了50%的平均效率。在5 MHz 3GPP驱动信号下使用简单的多项式数字预失真。

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