机译:具有三重四倍响应的FPGA实现中仲裁器PUF的可靠建模抗攻击认证
School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore;
Faculty of Computer Systems and Networks, Belarusian State University of Informatics and Radioelectronics, Minsk, Belarus;
School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore;
Field programmable gate arrays; Reliability; Authentication; Hardware; Servers; Machine learning; Resistance;
机译:FPGA实施挑战预处理结构仲裁器PUF专为机器学习攻击阻力而设计
机译:一种抗拒基于轻量级PUF的认证的抗性欺骗技术
机译:基于XOR仲裁器PUF及其变体的基于计算的基于计算的张量回归网络的建模攻击
机译:可靠性增强的抗攻击仲裁器PUF的FPGA实现
机译:基于 SR触发器 PUF 对 FPGA实现 硬件安全
机译:用于增强FPGA不可预测性的新型仲裁器PUF
机译:基于PUF的FPGA芯片识别和认证方法,具有增强的可靠性和建模攻击阻力