首页> 外文期刊>IEEE transactions on information forensics and security >Reliable and Modeling Attack Resistant Authentication of Arbiter PUF in FPGA Implementation With Trinary Quadruple Response
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Reliable and Modeling Attack Resistant Authentication of Arbiter PUF in FPGA Implementation With Trinary Quadruple Response

机译:具有三重四倍响应的FPGA实现中仲裁器PUF的可靠建模抗攻击认证

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Field programmable gate array (FPGA) is a potential hotbed for malicious and counterfeit hardware infiltration. Arbiter-based physical unclonable function (A-PUF) has been widely regarded as a suitable lightweight security primitive for FPGA bitstream encryption and device authentication. Unfortunately, the metastability of flip-flop gives rise to poor A-PUF reliability in FPGA implementation. Its linear additive path delays are also vulnerable to modeling attacks. Most reliability enhancement techniques tend to increase the response predictability and ease machine learning attacks. This paper presents a robust device authentication method based on the FPGA implementation of a reliability enhanced A-PUF with trinary digit (trit) quadruple responses. A two flip-flop arbiter is used to produce a trit for metastability detection. By considering the ordered responses to all four combinations of first and last challenge bits, each quadruple response can be compressed into a quadbit that represents one of the five classes of trit quadruple response with greater reproducibility. This challenge-response quadruple classification not only greatly reduces the burden of error correction at the device but also enables a precise A-PUF model to be built at the server without having to store the complete challenge-response pair (CRP) set for authentication. Besides, the real challenge to the A-PUF is generated internally by a lossy, nonlinear, and irreversible maximum length signature generator at both the server and device sides to prevent the naked CRP from being machine learned by the attacker. The A-PUF with short repetition code of length five has been tested to achieve a reliability of 1.0 over the full operating temperature range of the target FPGA board with lower hardware resource utilization than other modeling attack resilient strong PUFs. The proposed authentication protocol has also been experimentally evaluated to be practically secure against various machine learning attacks including evolutionary strategy covariance matrix adaptation.
机译:现场可编程门阵列(FPGA)是恶意和伪造硬件渗透的潜在温床。基于仲裁器的物理不可克隆功能(A-PUF)被广泛认为是FPGA比特流加密和设备认证的合适轻量级安全原语。不幸的是,触发器的亚稳定性会导致FPGA实施中A-PUF的可靠性下降。它的线性附加路径延迟也容易受到建模攻击的影响。大多数可靠性增强技术倾向于提高响应的可预测性并缓解机器学习攻击。本文提出了一种可靠的设备身份验证方法,该方法基于具有三位数字(trit)四重响应的可靠性增强型A-PUF的FPGA实现。两个触发器仲裁器用于产生用于亚稳检测的三叉戟。通过考虑对第一个和最后一个挑战位的所有四个组合的有序响应,可以将每个四重响应压缩为一个四位,该四位代表具有更高重现性的五组三联四重响应中的一种。这种质询-响应四重分类不仅大大减轻了设备上错误纠正的负担,而且还使得无需在服务器上构建用于身份验证的完整质询-响应对(CRP)即可在服务器上构建精确的A-PUF模型。此外,对A-PUF的真正挑战是在服务器和设备端内部由有损,非线性且不可逆的最大长度签名生成器内部生成的,以防止攻击者通过机器学习裸露的CRP。经过测试,长度为5的短重复代码的A-PUF在目标FPGA板的整个工作温度范围内均达到1.0的可靠性,并且与其他具有建模攻击能力的强大PUF相比,其硬件资源利用率更低。提议的身份验证协议也已经过实验评估,可以针对各种机器学习攻击(包括进化策略协方差矩阵自适应)进行实际安全保护。

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