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An Extended Building-In Reliability Methodology on Evaluating SRAM Reliability by Wafer-Level Reliability Systems

机译:晶圆级可靠性系统评估SRAM可靠性的扩展建筑物可靠性方法

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Advancement in integrated circuit (IC) brings a series of challenges on product reliability. In order to meet these challenges and fulfill customers' requirements, we introduced the methodology of building-in reliability (BIR) into whole stages during IC manufacturing. The wafer-level reliability (WLR) is an essential element of the BIR system. Significant amount of costs, resources, and times are saved from the early detections on reliability deficiencies at design and development stages. After successful mass production, hidden reliability risks can also be timely identified before shipment. Currently, the process reliability has been successfully evaluated by WLR platform. However, the product reliability, which covers much wider reliability factors, has not been effectively covered by WLR. Currently, we still rely on the conventional package-level reliability (PLR) tests to assess product reliability. In this paper, we report how the classical static random access memory (SRAM) is transplanted into the WLR system, which serves as an efficient platform to detect reliability weakness. In our extended BIR methodology, by reasonable test structure and pattern designs, proper electric parameters selections, test methods optimizations, we can thoughtfully consider inherent failure mechanisms and process fluctuations in order to build quantitative reliability models, which are essential to our proposed system. The quantitative reliability model was not seen in the similar WLR approaches and this may explain why these previous proposals failed. Finally, we report the obtained robust correlations between single-bit cell wear-out and package-level SRAM degradations, which is further validated by conventional HTOL tests. Our approaches provide opportunities not only on early detecting reliability weakness, but also on reliability assurance after product deliveries. These two contributions are essential and especially crucial for advanced technology developments.
机译:集成电路(IC)的进步为产品可靠性带来了一系列挑战。为了满足这些挑战和满足客户的要求,我们在IC制造期间介绍了建立可靠性(BIR)的建立可靠性(BIR)的方法。晶片级可靠性(WLR)是BIR系统的必要因素。从设计和开发阶段的可靠性缺陷的早期检测,将大量的成本,资源和时间保存。在成功的批量生产后,也可以在发货前及时确定隐藏的可靠性风险。目前,WLR平台已成功评估流程可靠性。然而,产品可靠性涵盖了更广泛的可靠性因素,WLR尚未有效地覆盖。目前,我们仍然依靠传统的包级可靠性(PLR)测试来评估产品可靠性。在本文中,我们报告了经典静态随机存取存储器(SRAM)如何移植到WLR系统中,该系统用作检测可靠性弱点的有效平台。在我们的扩展BIR方法中,通过合理的测试结构和图案设计,适当的电参数选择,测试方法优化,我们可以仔细考虑固有的故障机制和过程波动,以便构建定量可靠性模型,这对我们所提出的系统至关重要。在类似的WLR方法中没有看到定量可靠性模型,这可以解释为什么这些先前的建议失败。最后,我们报告了单位细胞磨损和封装级SRAM降解之间获得的鲁棒相关性,其通过常规HTOL测试进一步验证。我们的方法不仅提供了在早期检测可靠性弱点的机会,而且提供了产品交付后的可靠性保证。这两个贡献对于先进技术发展至关重要,尤其重要。

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