...
【24h】

Verification algorithms for VLSI synthesis

机译:VLSI综合的验证算法

获取原文
获取原文并翻译 | 示例
   

获取外文期刊封面封底 >>

       

摘要

A description is given of a theory for, and the application of, a general algorithm for determining whether a given multilevel Boolean function is a tautology or whether two given multilevel Boolean functions are equivalent. Four specific cases of this general algorithm are examined. These are termed the flattening method, the don't-care method, the simulation method, and the algebraic string comparison method. A single unifying algorithm frame is given for the implementation of any of these four methods, depending on parameterization. Experimental results are given which indicate that, with the exception of the don't-care method, each of these methods has a problem class in which it is clearly superior to the others. The primary application of these algorithms is as a verification tool for silicon compilation systems. However, these algorithms are also being used as the foundation for multilevel logic minimization and automatic test pattern generation programs.
机译:给出了用于确定给定的多级布尔函数是否是重言式或两个给定的多级布尔函数是否等效的通用算法的理论及其应用的描述。研究了该通用算法的四个特定情况。这些被称为展平方法,无关方法,模拟方法和代数字符串比较方法。根据参数设置,为实现这四种方法中的任何一种给出了一个统一的算法框架。给出的实验结果表明,除了“不在乎”方法之外,这些方法中的每一种都具有明显优于其他方法的问题类别。这些算法的主要应用是作为硅编译系统的验证工具。但是,这些算法也被用作多级逻辑最小化和自动测试模式生成程序的基础。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号