Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence

摘要

As technology advances, the metal width decreases while the global wire length increases. This trend makes the resistance of the power wire increase substantially. Furthermore, the threshold voltage scales nonlinearly, raising the ratio of the threshold voltage to the supply voltage and making the voltage (IR) drop in the power/ground (P/G) network a serious problem in modern IC design. Traditional P/G network-analysis methods are often very computationally expensive, and it is, thus, not feasible to cosynthesize P/G network with floorplan. To make the cosynthesis feasible, we need not only an efficient, effective, and flexible floorplanning algorithm but also a very efficient yet sufficiently accurate P/G network-analysis method. In this paper, we present a method for floorplan and P/G network cosynthesis based on an efficient P/G network-analysis scheme and the B*-tree floorplan representation. We integrate the cosynthesis into a commercial design flow to develop an effective power-integrity (IR drop)-driven design methodology. Experimental results based on a real-world circuit design and the MCNC benchmarks show that our design methodology successfully fixes the IR-drop errors earlier at the floorplanning stage and, thus, enables the single-pass design convergence