POWER-AND-GROUND (PG) NETWORK CHARACTERIZATION AND DISTRIBUTED PG NETWORK CREATION FOR HIERARCHICAL CIRCUIT DESIGNS

摘要

A chip layout can include a top-level portion and a set of blocks. The power-and-ground (PG) network for the chip layout can be specified by a set of chip-level PG constraints that is defined using a PG constraint definition language. The set of chip-level PG constraints can be characterized into new sets of PG constraints that correspond to smaller regions of the chip layout, e.g., a set of top-level PG constraints that corresponds to the top-level portion, and a set of block-level PG constraints for each block in the set of blocks. The new sets of PG constraints can then be provided to one or more instances of a PG compiler that executes on one or more processors to create the PG network for the chip layout.