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Simultaneous Constrained Pin Assignment and Escape Routing Considering Differential Pairs for FPGA-PCB Co-Design

机译:同时考虑差分对的同时约束引脚分配和转义布线的FPGA-PCB协同设计

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摘要

With the increasing complexity of circuit design in recent years, the pin assignment and escape routing problems for field-programmable gate array (FPGA) on a printed circuit board (PCB) have become greatly difficult due to the fast increase in pin count and density. Most existing works only focus on either the FPGA pin assignment problem or the PCB escape routing problem independently, but cannot handle them simultaneously. In this paper, we propose an integer linear programming based method to simultaneously solve the problem of pin assignment and escape routing for FPGA-PCB co-design. Moreover, differential pairs and single-ended signals are handled together optimally to minimize the total wirelength in escape routing. Encouraging experimental results are shown to support our approach showing reduction in the number of PCB routing layers and/or wirelength.
机译:近年来,随着电路设计的复杂性增加,由于引脚数和密度的快速增加,印刷电路板(PCB)上的现场可编程门阵列(FPGA)的引脚分配和逃逸布线问题变得非常困难。现有的大多数作品只专注于FPGA引脚分配问题或PCB转义布线问题,但无法同时处理。在本文中,我们提出了一种基于整数线性规划的方法,以同时解决FPGA-PCB协同设计的引脚分配和逃逸布线问题。此外,差分对和单端信号被最佳地处理在一起,以最小化逃生布线中的总线长。令人鼓舞的实验结果表明,可以支持我们的方法,减少PCB布线层的数量和/或线长。

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