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Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign

机译:FPGA-PCB协同设计的同时约束引脚分配和转义布线

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With the increasing complexity of circuit design in recent years, the pin assignment and escape routing problems for FPGA on a PCB have become greatly difficult due to the fast increase in pin count and density. Most existing works only focus on either the FPGA pin assignment problem or the PCB escape routing problem independently but cannot handle them simultaneously. In this paper, we propose an integer linear programming (ILP) based method to simultaneously solve the pin assignment and escape routing problems for FPGA-PCB code sign. Because of the underlying network structure of our formulation, we can solve the problem efficiently. Experimental results demonstrate that our method can achieve an average 54.5% wire length improvement over the common two-stage approach.
机译:近年来,随着电路设计复杂性的增加,由于引脚数和密度的快速增加,PCB上FPGA的引脚分配和逃逸布线问题变得非常困难。现有的大多数作品只专注于FPGA引脚分配问题或PCB逃逸布线问题,但无法同时处理。在本文中,我们提出了一种基于整数线性规划(ILP)的方法,以同时解决FPGA-PCB代码符号的引脚分配和转义布线问题。由于我们制定的基本网络结构,我们可以有效地解决问题。实验结果表明,与常规的两步法相比,我们的方法可将线长平均提高54.5%。

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