机译:高效视频编码中分数像素插值的可重构硬件架构
Informatics Institute, Federal University of Rio Grande do Sul, Porto Alegre, Brazil;
Computer architecture; Decoding; Encoding; Engines; Hardware; Interpolation; Video coding; Accelerators; HEVC; Hardware Architecture; Interpolation Filter; Reconfigurable Data Paths; hardware architecture; high efficient video coding (HEVC); interpolation filter; reconfigurable data paths;
机译:用于高效视频编码的分数运动估计插值的VLSI实现
机译:用于高效率视频编码的高通量样本自适应偏移硬件架构
机译:高效视频编码的硬件友好高级运动矢量预测方法及其架构设计
机译:HDTV视频编解码器中子像素插值的硬件实现
机译:可重新配置的Turbo编码器/解码器仿真器的高效硬件实现。
机译:可重配置硬件中的峰值排序的高效架构
机译:用于高清视频的可重构帧插值硬件架构