A VLSI signal processor with complex arithmetic capability

摘要

The PSI, a programmable digital signal processor that includes the full complex computation mode, is presented. A complex parallel multiplier is derived from a real multiplier by adding pipeline stages. The pipeline introduced in the arithmetic unit fits the parallel nature of complex multiplications that require four real multiplications simultaneously. The internal architecture is optimized for a set of kernel algorithms currently used in signal-processing applications. Several algorithms are presented that exemplify the high performance of the PSI for complex signal processing. It is shown that the external architecture of the PSI allows one to realize efficient multiprocessor applications.