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Design and Analysis of an Always-ON Input-Biased pA-Current Sub-nW mV-Threshold Hysteretic Comparator for Near-Zero Energy Sensing

机译:用于几乎为零的能量感应的常开输入偏置的pA电流低于nW mV阈值磁滞比较器的设计与分析

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This paper presents the design and analysis of an always-ON comparator capable of detecting mV-range input voltage signals reliably with sub-nW power consumption. The comparator compares the two pA currents generated by current mirrors biased by the mV-range input signal. With the input signal near zero at the standby mode, the comparator consumes near-zero energy. A positive feedback is introduced to accelerate the output signal transition to the supply or the ground and to generate the hysteresis to tolerate the noise in the input signal. The comparator threshold and the amount of hysteresis are programmed using control signals to adjust the current mirror transistor sizes. Analytic expressions of comparator characteristics are derived using circuit theory and subthreshold transistor models, and have been validated using simulation and measurement. A prototype comparator implementing these ideas was designed and fabricated in a standard 65-nm CMOS process. Chip measurements have shown that the comparator achieved programmable thresholds from 27 to 46.5 mV with energy per switching from 1.9 to 2.4 nJ using four control bits. The measured power consumption is 270 pW at the input signal of 0.1 mV with the frequency of 10 Hz.
机译:本文介绍了一种始终接通的比较器的设计和分析,该比较器能够以低于nW的功耗可靠地检测mV范围的输入电压信号。比较器比较由mV范围输入信号偏置的电流镜产生的两个pA电流。在待机模式下,输入信号接近于零时,比较器消耗的能量接近于零。引入正反馈可加速输出信号向电源或地面的过渡,并产生滞后现象以容忍输入信号中的噪声。使用控制信号对比较器阈值和滞后量进行编程,以调整电流镜晶体管的尺寸。利用电路理论和亚阈值晶体管模型推导了比较器特性的解析表达式,并已通过仿真和测量进行了验证。实现这些想法的原型比较器是在标准的65纳米CMOS工艺中设计和制造的。芯片测量表明,比较器通过四个控制位,每次开关的能量从1.9到2.4 nJ,实现了27到46.5 mV的可编程阈值。在频率为10 Hz的0.1 mV输入信号下测得的功耗为270 pW。

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