A Low Energy-Noise 65nm CMOS Switched-Capacitor Resistive-Bridge Sensor Interface

摘要

A low energy-noise switched-capacitor (SC) sensor interface for resistive bridge sensor is presented. The SC amplifier achieves low-power metric with two operating modes using operation-phase-dependent biasing and compensation scheme in the op-amp design. This novel op-amp works in high-bandwidth high-power mode to sample the bridge signal for 13μs twice and in low-bandwidth low-power mode for 474μs over 500μs measurement interval. To further reduce the power of the SC amplifier in system level, a SC level-shift design is adopted. Regarding offset calibration, a capacitor divider based trimming scheme is implemented to generate the mid-point DC output voltage under the constraint of the feedback capacitor size. Implemented in 65 nm CMOS, the SC interface together with the regulator, voltage reference and trimming circuit occupies an area of 0.358 mm2. For the first test setup utilizing Half Wheatstone Bridge, the proposed SC amplifier consumes 12.3μW at 1 V regulated supply with a 2 kHz system clock. The measured Signal-to-Noise Ratio (SNR) of SC circuit is 55.6 dB. In the second test setup using a commercial sensor with 0.092 mV/kPa sensitivity, the interface has demonstrated the sensing function with sensitivity of 3.52 mV/kPa. Finally, compared to the representative prior-arts, this work has achieved the best energy-noise figure-of-merit at identical fractional resistance change.