A Ripple Reduction Method for Switched-Capacitor DC–DC Voltage Converter Using Fully Digital Resistance Modulation

Fu-Yan Xie; Bing-Chen Wu; Tsung-Te Liu

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A Ripple Reduction Method for Switched-Capacitor DC–DC Voltage Converter Using Fully Digital Resistance Modulation

机译：使用全数字电阻调制的开关电容DC-DC电压转换器的纹波抑制方法

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摘要

The output ripple of switched-capacitor dc–dc voltage converter (SCVC) severely degrades the energy efficiency, performance, and robustness of the VLSI system. In this paper, a fully digital resistance modulation (FDRM) technique is proposed to reduce the

机译：开关电容器DC-DC电压转换器（SCVC）的输出纹波严重降低了VLSI系统的能效，性能和耐用性。本文提出了一种全数字电阻调制（FDRM）技术，以减少

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来源
《IEEE transactions on circuits and systems . I , Regular papers》 |2019年第9期|3631-3641|共11页
作者
Fu-Yan Xie; Bing-Chen Wu; Tsung-Te Liu;
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作者单位

Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan;

Graduate Institute of Electronics Engineering National Taiwan University;

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原文格式 PDF
正文语种 eng
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关键词
Switches; Loading; Clocks; Resistance; Modulation; Prototypes; Reliability;

机译：开关;加载;时钟;抵抗性;调制;原型;可靠性;

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1. A Ripple Reduction Method for Switched-Capacitor DC–DC Voltage Converter Using Fully Digital Resistance Modulation [J] . Fu-Yan Xie, Bing-Chen Wu, Tsung-Te Liu IEEE transactions on circuits and systems . I , Regular papers . 2019,第9期

机译：使用全数字电阻调制的开关电容DC-DC电压转换器的纹波抑制方法
2. A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage [J] . Xin ZHANG, Yu PU, Koichi ISHIDA, IEICE Transactions on Electronics . 2011,第6期

机译：具有脉冲密度和宽度调制（PDWM）的可变输出电压开关电容器DC-DC转换器，可在低输出电压下降低57％的纹波
3. A 1-V Input, 0.2-V to 0.47-V Output Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction [J] . Xin ZHANG, Yu PU, Koichi ISHIDA, 電子情報通信学会技術研究報告. 集積回路. Integrated Circuits and Devices . 2010,第344期

机译：具有脉冲密度和宽度调制（PDWM）的1V输入，0.2V至0.47V输出的开关电容器DC-DC转换器，纹波减小了57％
4. A 1-V input, 0.2-V to 0.47-V output switched-capacitor DC-DC converter with pulse density and width modulation (PDWM) for 57 ripple reduction [C] . Xin Zhang, Yu Pu, Ishida K., 2010 IEEE Asian Solid State Circuits Conference . 2010

机译：具有脉冲密度和宽度调制（PDWM）的1V输入，0.2V至0.47V输出的开关电容器DC-DC转换器，可减少57％的纹波
5. Analytical modeling and design of high efficiency fully-integrated switched-capacitor DC-DC converters and a high-voltage current regulator [D] . Veerabathini, Anurag. 2018

机译：高效全集成开关电容DC-DC转换器的分析建模与设计和高压电流调节器
6. A High Voltage Ratio and Low Ripple Interleaved DC-DC Converter for Fuel Cell Applications [O] . Long-Yi Chang, Kuei-Hsiang Chao, Tsang-Chih Chang 2012

机译：用于燃料电池应用的高电压比和低纹波交错式DC-DC转换器
7. Reproducing single-carrier digital modulation schemes for VLC by controlling the first switching harmonic of the dc-dc power converter output voltage ripple [O] . Rodríguez Méndez Juan, Fernández Miaja Pablo, González Lamar Diego, 2018

机译：通过控制DC-DC电源转换器输出电压纹波的一次开关谐波来再现VLC的单载波数字调制方案

A Ripple Reduction Method for Switched-Capacitor DC–DC Voltage Converter Using Fully Digital Resistance Modulation

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