机译:直接射频采样接收器中带通采样四通道时间交错ADC的数字失配校正
Department of Electrical and Electronic Systems Engineering Osaka Institute of Technology Osaka Japan;
Division of Electrical and Electronic Engineering Graduate School of Engineering Osaka Institute of Technology Osaka Japan;
Department of Electrica;
Receivers; Radio frequency; Finite impulse response filters; Automatic generation control; Adders; Mixers; Convergence;
机译:A 5 GS / S 158.6-MW 9.4-ENOB被动采样时间交错的三级流水线-SAR ADC,具有28-NM CMOS中的模拟数字校正
机译:低复杂度数字背景校准算法,用于校正时间交错ADC中的时序失配
机译:数字背景校准算法及其对时间交错ADC定时失配校正的FPGA实现
机译:Direct-RF采样接收器中用于时间交错ADC的多相抽取滤波器
机译:具有毫米波采样时钟的可调RF带通delta-sigma数字接收器
机译:数字化测定的设计和解释:样品和样品来源中目标的浓度
机译:具有IF采样和数字定时校正的多速率接收器设计