LOW-POWER DESIGN APPROACH OF 11F04 256-KBYTE EMBEDDED SRAM FOR THE SYNERGISTIC PROCESSOR ELEMENT OF A CELL PROCESSOR

摘要

THE SYNERGISTIC PROCESSOR ELEMENT is A NEW ARCHITECTURE ORIENTED FOR MULTIMEDIA AND STREAMING PROCESSING. IN THIS ARCHITECTURE, THE MEMORY IS NOT A CACHE BUT A PRIVATE OR SCRATCH PAD MEMORY. SUCH A MEMORY IS SIMPLE AND NEEDS TO BE HIGH-FREQUENCY AND LARGE SPACE IN LOW-POWER. THIS DESIGN USES AN 11 FAN-OUT OF FOUR (11F04), SIX-CYCLE, FULLY PIPELINED, EMBEDDED 256-KBYTE SRAM FOR THIS PURPOSE. THE DESIGN'S MEMORY IS NOT ONE HARD MACRO, BUT A GROUP OF CUSTOM MACROS PHYSICALLY DISTRIBUTED TO OPTIMIZE THE PIPELINE.