DESIGN OF A HIGH-SPEED OPTICAL INTERCONNECT FOR SCALABLE SHARED-MEMORY MULTIPROCESSORS

摘要

THE ARCHITECTURE PROPOSED HERE REDUCES REMOTE MEMORY ACCESS LATENCY BY INCREASING CONNECTIVITY AND MAXIMIZING CHANNEL AVAILABILITY FOR REMOTE COMMUNICATION. IT ALSO PROVIDES EFFICIENT AND FAST UNICAST, MULTICAST, AND BROADCAST CAPABILITIES, USING A COMBINATION OF AGGRESSIVELY DESIGNED MULTIPLEXING TECHNIQUES. SIMULATIONS SHOW THAT THIS ARCHITECTURE PROVIDES EXCELLENT INTERCONNECT SUPPORT FOR A HIGHLY SCALABLE, HIGH-BANDWIDTH, LOW-LATENCY NETWORK.