Design and Characterization of Null Convention Self-Timed Multipliers

摘要

For the past two decades, digital design has focused primarily on synchronous, clocked architectures. However, because clock rates have significantly increased while feature size has decreased, clock skew has become a major problem. To achieve acceptable skew, high-performance chips must dedicate increasingly larger portions of their area to clock drivers, thus dissipating increasingly higher power, especially at the clock edge, when switching is most prevalent. As this trend continues, the clock is becoming more difficult to manage, causing renewed interest in asynchronous digital design. Researchers have demonstrated that correct-by-construction asynchronous paradigms, particularly null convention logic (NCL), require less power, generate less noise, produce less electromagnetic interference, and allow easier reuse of components than their synchronous counterparts, without compromising performance. Furthermore, we expect these paradigms to allow much greater flexibility in the design of complex circuits such as SoCs. Because these circuits are delay insensitive, they should drastically reduce the effort required to ensure correct operation under all timing scenarios, compared to equivalent synchronous designs. Also, the self-timed nature of correct-by-construction SoCs should allow designers to reuse previously designed and verified functional blocks in subsequent designs, without significant modifications or retiming effort within a reused functional block. Such SoCs might also provide simpler interfacing between the digital core and nontraditional functional blocks. One of the first tasks necessary to help integrate NCL into the semiconductor design industry is to develop and characterize the key components of a reusable-design library. Of fundamental importance are arithmetic circuits, including the multipliers we describe in this article and the ALUs we described elsewhere. Here, we present 4-bit×4-bit unsigned multipliers that we designed using the delay-insensitive NCL paradigm. They represent bit-serial, iterative, and fully parallel multiplication architectures. The figures depicting each multiplier component are available at http://www.ece.umr.edu/～smithsco.