The authors outline a design methodology for the realisation of digital filtering structures with significantly reduced numbers of elementary arithmetic operations. The directed acyclic graphs which result from the design algorithms completely describe the filter arithmetically and may be mapped directly onto hardware or software realisations. Vertex rearrangement, retiming and edge elimination techniques are presented which facilitate the generation of a logical graph with an efficient allocation of pipeline registers. An example of the technique is given for a bit-serial realisation employing a bit-level pipeline.
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